Field of the Invention
The present invention relates to the field of three-dimensional integrated circuits and more particularly to devices and the fabrication thereof of three-dimensional integrated circuits using direct wafer bonding.
Description of the Related Art
Semiconductor integrated circuits (ICs) are typically fabricated into and on the surface of a silicon wafer resulting in an IC area that must increase as the size of the IC increases. Continual improvement in reducing the size of transistors in ICs, commonly referred to as Moore's Law, has allowed a substantial increase in the number of transistors in a given IC area. However, in spite of this increased transistor density, many applications require an increase in total IC area due to a greater increase in required transistor count or an increase in the number of lateral interconnections required between transistors to achieve a specific function. The realization of these applications in a single, large area IC die typically results in a reduction in chip yield and, correspondingly, increased IC cost.
Another trend in IC fabrication has been to increase the number of different types of circuits within a single IC, more commonly referred to as a System-on a-Chip (SoC). This fabrication typically requires an increase in the number of mask levels to make the different types of circuits. This increase in mask levels typically also results in a reduction in yield, and correspondingly, increased IC cost. A solution to avoiding these undesired decreases in yield and increases in cost is to vertically stack and vertically interconnect ICs. These ICs can be of different size, come from different size wafers, comprise different functions (i.e., analog, digital, optical), be made of different materials (i.e., silicon, GaAs, InP, etc.). The ICs can be tested before stacking to allow Known Good Die (KGD) to be combined to improve yield. The economic success of this vertical stacking and vertical interconnect, or three-dimensional 3D SoC, approach depends on the yield and cost of the stacking and interconnection being favorable compared to the yield and cost associated with the increased IC or SoC area. A manufacturable method for realizing this approach is to vertically stack separately fabricated ICs using direct bonding where the direct bonding surface preparation uses conventional wafer fabrication techniques, for example, metal deposition, dielectric deposition, chemo-mechanical polishing, wafer thinning, photolithography masking, and via etching. A further advantage of using direct bonding for 3D SoC fabrication is the ability to achieve a scalable density of vertical interconnections between different layers or tiers of the stack as a result of the direct bond process.
Direct bonding requires a substantially planar surface that does not result from typical IC wafer fabrication. Achieving an adequate wafer planarization can thus be a substantial element of cost in a direct bond process. It is thus desirable to have a device that comprises a structure and a method to fabricate said structure requiring a minimum cost to achieve this required surface planarity.
Metal direct bonding includes methods and devices for forming 3D structures wherein electrically isolated electrical interconnections can be made across a bond interface which can be formed by aligning and placing two surfaces of two elements into direct contact. Each surface can have insulating and conducting portions and aligned conducting portions can result in a 3D electrical interconnection across the bond interface, and aligned insulating portions can isolate 3D electrical interconnections from other 3D electrical interconnections.
The details of making of a 3D electrical interconnections across the bond interface depends on the relative planarity of the insulating and conducting portions. For example, if the conducting portions are higher than the insulating portions, a 3D interconnection can be made by simply placing two surfaces into contact, for example if the there is not a native oxide on the conducting portion preventing a 3D interconnection and the extension of the conducting portion above the insulating portion is sufficiently small that insulating portions can also bond in direct contact with surface compliance. 3D interconnections may also not be made by simply placing two surfaces into contact, for example if the conducting portions are lower than the insulating portions such that the conducting portions do not come into contact when the surfaces are place together. In this example, 3D interconnections can be made with a slight increase in temperature due to the coefficient of thermal expansion (CTE) difference between the conducting and insulating portion and an adequate bond energy between insulating components that sufficiently compresses the conducting components during heating if the elements are of standard thickness. If the CTE of the elements are comparable, the slight increase in temperature to make a connection can be accommodated by the bond energy of the insulating portions that are in contact and the stiffness of the element. If the CTE of the elements are not comparable, for example for some heterogeneous material combinations, high bond energy of the insulating portions in contact can result in fracture of one or both of the elements during the heating used to make the 3D interconnections. This fracture can be avoided by thinning one of the elements sufficiently prior to heating. This thinning increases the compliance of the element by reducing its stiffness so that it can accommodate the CTE difference of the elements. Thinning to accommodate this difference in CTE can result in a reduced stiffness of the element such that compression is not adequate to make a 3D interconnection.